1. Field of Invention
The present invention relates to a flash EPROM structure. More particularly, the present invention relates to a method for forming ETOX cells (Intel Type Flash EPROM Cells) using a self-aligned source etching process.
2. Description of Related Art
Erasable programmable ROM (EPROM) is a type of memory circuit commonly used in computer and electronic products. The advantage of EPROM is that stored data or programs will not be erased under normal circumstances. However, if the data or program really need to be erased, this can be done by shining an ultraviolet (UV) light source onto the EPROM for a period. Once the data or programs have been removed, new data or programs can then be entered and stored. Because all the old data and programs are lost during the EPROM erasing process and everything needs to be re-entered from scratch, much time is wasted in the process. In view of this, Intel Corp. has developed and introduced a kind of memory known as flash EPROM to the market. Data in the flash EPROM will not be completely wiped out in a single erase operation. Instead, data can be locally amended block by block. When the dimensions of flash EPROM are miniaturized, a self-aligned source etching process becomes the obvious choice for forming the ETOX cells. However, in a conventional method of producing ETOX cells, the plasma-etching operation will damage the oxide/nitride/oxide (ONO) layer. This will result in charge retention and reliability problems.
FIG. 1A is a layout diagram for a collection of ETOX cells formed by the conventional self-aligned source etching process. As shown in FIG. 1A, the labeled items include floating gates 13, control gates 15, masks 18, field oxide layers 17, drain regions 16b and a common source region 16a, which is patterned out according to masks 18. The area labeled 9 within a dotted rectangle is the location of an ETOX cell.
FIG. 1B is a cross-section along line I-I' in FIG. 1A. As shown in FIG. 1B, the ETOX cell comprises a gate, a common source region 16a and a drain region 16b. The gate is a four-layered stack including a tunnel oxide layer 12, a floating gate 13, an ONO layer 14 and a controlling gate 15. The controlling gate 15 and the floating gate 13 together constitute a gate terminal. The common source region 16a and the drain region 16b are formed in a substrate 11 on each side of the gate.
FIG. 1C is a cross-section along line II-II' in FIG. 1A. As shown in FIG. 1C, a field oxide layer is formed above the substrate 11, and that the controlling gate 15 is formed above the field oxide layer 17.
FIGS. 2A and 2B are cross-sectional views showing the progression of manufacturing steps in the production of ETOX cell by a conventional self-aligned source etching process. The cross-sectional line along which FIGS. 2A and 2B are derived from is the same as in FIG. 1C. First, a substrate structure having gates 15 and field oxide layers 17 already formed thereon is provided. The substrate structure here is similar to the one shown in FIG. 1C. The only difference between them is that a common source region 16a has not been formed in the substrate structure in FIG. 2A. Then, a photomask 18 is formed to cover the substrate and patterned such that locations of the common source regions 16a are exposed to get ready for subsequent processing operations.
Next, with reference to FIG. 1A, FIG. 1C and FIG. 2B, the exposed field oxide layer 17 is etched using a dry etching method having a high selectivity ratio. Thereafter, the photomask 18 is removed. This is followed by ion doping operations to form the common source region 16a and the drain region 16b. Because subsequent processes are familiar to those skilled in the art, detailed description is omitted here.
Because the conventional self-aligned source etching technique in forming the ETOX cells can easily damage the oxide/nitride/oxide layer of the gate, charge retention and reliability problems are quite common.
In light of the foregoing, there is a need in the art to improve the method of forming ETOX cells.